Modern electronic devices, especially semiconductor (SC) devices and integrated circuits (ICs) are at risk of damage due to electrostatic discharge (ESD) events. It is well known that electrostatic discharge from handling SC devices and ICs, by humans or machines or both, is a source of such excess voltage. Accordingly, it is commonplace to provide an ESD clamp (voltage limiting device) across the input/output (I/O) and other terminals of such SC devices and IC's.
FIG. 1 is a simplified schematic diagram of circuit 20 wherein ESD clamp 21 is placed between input/output (I/O) terminals 22 and ground or common terminal 23 of a SC device or IC to protect the other devices on the chip, that is, to protect circuit core 24 which is also coupled to I/O terminals 22 and common (e.g., “GND”) terminal 23. I/O terminals 22 may also be referred to more generally as “first terminals” 22 and include other functions in addition to input and output, and GND terminal 23 may also be referred to more generally as “second terminal” 23 and include other functions besides connection to a common or reference potential or bus. Zener diode symbol 21′ within ESD clamp 21 symbolically indicates that the function of ESD clamp 21 is to limit the voltage than can appear across circuit core 24 irrespective of the voltage existing at external terminals 22, 23. ESD clamp 21 may or may not include an actual Zener diode. As used herein, the abbreviation “GND” is intended to refer to the common or reference terminal of a particular circuit or electronic element, irrespective of whether it is actually coupled to an earth return and the abbreviation “I/O” is intended to include any terminals of the SC device or IC protected by an ESD clamp.
FIG. 2 is a simplified schematic diagram illustrating internal components of prior art ESD clamp 31 that is inserted in circuit 20 in place of ESD clamp 21. ESD clamp 31 comprises field effect transistor 25, having source 26, drain 27, gate 28, body contact 29, and parallel resistances 30, 32. Resistance 30 is coupled from gate 28 to node 34, which is in turn coupled to GND terminal 23 and source 26. Resistance 32 is coupled from body contact 29 of transistor 25 to node 34 which is in turn coupled to GND terminal 23 and source 26. When the voltage across terminals 22, 23 rises beyond a predetermined limit referred to as the “trigger voltage Vt1”, transistor 25 turns on, desirably clamping the voltage across terminals 22, 23 at a level below a value capable of damaging circuit core 24. The lateral size of transistor 25 is chosen to be capable of sinking the expected ESD current without allowing the voltage across terminals 22, 23 to rise above the trigger voltage Vt1. Such ESD clamps are well known in the art. FIG. 3 is an illustration of a typical current-voltage characteristic of an ESD clamp, where voltage Vt1 is referred to as the trigger voltage and voltage Vh is referred to as the holding voltage.